STU

25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70

25-bit configurable registered buffer with SSTL_18 inputs & outputs 96-LFBGA 0 to 70

28-bit to 56-bit registered buffer with address-parity test 176-NFBGA -40 to 85

IC,MEMORY DRIVER,CMOS,BGA,96PIN,PLASTIC

25-Bit Configurable Registered Buffer With SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70

IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96, FF/Latch

SPECIALTY TELECOM CIRCUIT, DMA30, DIP-30

25-bit configurable registered buffer with address-parity test 96-NFBGA -40 to 85

25-Bit Configurable Registered Buffer With SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70

28-bit to 56-bit registered buffer with address-parity test for heavily loaded DDR2 registered DIMMs 176-NFBGA -40 to 85

IC,MEMORY DRIVER,CMOS,BGA,96PIN,PLASTIC

SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96

SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96

25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70

25-Bit Configurable Registered Buffer w/Address-Parity Test 96-LFBGA -40 to 85

IC SPECIALTY TELECOM CIRCUIT, Telecom IC:Other

28-Bit to 56-Bit Registered Buffer with Address-Parity Test 160-NFBGA -40 to 85

25-bit configurable registered buffer with SSTL_18 inputs & outputs 96-LFBGA 0 to 70

410-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs 96-NFBGA -40 to 85

500-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs 96-NFBGA 0 to 70